1. Technical Field
The present invention relates to electronic memory devices, and more particularly, to semiconductor memory devices suitable for use as a memory devices.
2. Related Art
Semiconductor memory devices are well known and commonly found in a variety of electronic devices. Most semiconductor memory devices can be classified as either volatile or nonvolatile. A volatile memory device requires power in order to maintain the stored data, while a nonvolatile memory device can retain stored data even in the absence of power.
A well known type of nonvolatile memory is flash memory. A typical flash memory includes a memory cell array in which memory cells are arranged in rows and columns. Each memory cell includes a floating gate field-effect transistor. The logic state of a memory cell depends on the threshold voltage of the transistor, which in turn depends on the number of electrons in the floating gate of the transistor. Electrons in the floating gate partially cancel the electric field from the control gate, thereby modifying the threshold voltage of the transistor. Thus, the logic state of a flash memory state can be controlled by controlling the number of electrons in the floating gate of the transistor.
A flash memory cell can be programmed and erased in order to write respective logic states to the memory cell. The program and erase operations correspond to write operations for respective logic states, which correspond to respective threshold voltages. For convenience, the threshold voltages will simply be referred to as high and low threshold voltages, with it being understood that the high threshold voltage is relatively higher than the low threshold voltage by some detectable voltage margin. The number of electrons stored in the floating gate of a memory cell transistor can be altered by applying a strong electric field between the control gate and at least one of the source, drain, and substrate of the field-effect transistor in order to remove or accumulate electrons in the floating gate. An “erase” operation can be an operation where electrons are removed from the floating gate, thereby reducing the threshold voltage of the memory cell transistor to the low threshold voltage. A “program” operation can be an operation where electrons are accumulated in the floating gate, thereby increasing the threshold voltage of the memory cell transistor to the high threshold voltage. Since erased and programmed memory cells can be readily distinguished due to the difference in threshold voltages, the erased and programmed memory cells can be used to represent different logic states. For example, an erased memory cell can be representative of a logic state “1,” while a programmed memory cell can be representative of a logic state “0.”
FIG. 1 shows a flowchart of a conventional erase operation used in a flash memory. In flash memories, blocks of memory cells referred are typically erased together as a group. A block represents a number of memory cells that can be erased simultaneously during an erase operation. A conventional erase operation for erasing a block of memory cells generally includes a pre-program cycle 110, an erase cycle 120, and a soft program cycle 130.
During the pre-program cycle 110, the floating gates of all of the memory cells in a selected block are programmed to have approximately the same amount of electrons so that all of the memory cells in the selected block have approximately the same threshold voltage. The pre-program cycle 110 includes a pre-program process 112 and a pre-program verify process 114. During the pre-program process 112, a pre-program pulse is applied to all of the memory cells in the block. During the pre-program verify process 114, all of the memory cells in the block are checked to verify that their respective threshold voltages are approximately the same after application of the pre-program pulse. If an insufficient number of memory cells have the desired threshold voltage, then the pre-program process 112 is repeated. Otherwise, the operation continues to the erase cycle 120.
During the erase cycle 120, all of the memory cells in the block are erased by applying an erase pulse to the control gates of all the memory cells in the block in order to remove electrons from the floating gates of all the memory cells in the block. The erase cycle 120 includes an erase process 122 and an erase verify process 124. During the erase process 122, an erase pulse is applied to all of the memory cells in the block. During the erase verify process 124, all of the memory cells in the block are checked to verify whether they have been erased. If the number of erased memory cells is sufficient, then the block is regarded as being erased successfully. If the block fails to pass the erase verify process 124, all of the memory cells in the block are erased again by applying another erase pulse. In some systems, a voltage-stepping procedure is employed wherein the voltage is increased for each iteration of the erase cycle 120. In other systems, a time-stepping procedure is employed wherein the pulse width of the erase pulse is increased for each iteration of the erase cycle 120.
Since it is common for threshold voltages of memory cells to vary within any given block, the erase-pulse voltage required for erasing different memory cells can vary. During later iterations of the erase cycle 120, the application of an erase pulse with a relatively larger voltage or longer pulse width can result in over-erasure of some memory cells. An over-erased memory cell can cause other memory cells coupled to the same column as the over-erased memory cell to be regarded as erased cells, even though they may be programmed. Therefore, over-erased cells are typically repaired using the soft program cycle 130.
During the soft program cycle 130, over-erased memory cells in the block are detected and repaired. The soft program cycle 130 includes a soft program process 132 and a soft program verify process 134. During the soft program process 132, all of the memory cells in the block are checked to determine whether any of the memory cells are over-erased. If an over-erased memory cell is detected, it is repaired by applying a soft-program pulse. The soft-program pulse is different from a normal programming pulse in that the wordline and bitline voltages for the soft-program pulse are lower than the wordline and bitline voltages for the normal programming pulse. Also, unlike a programming pulse that is performed for programming a memory cell, a soft-program pulse is performed for erasing an over-erased memory cell. For example, a normal programming pulse can use a wordline voltage of 3.0-4.0V and a bitline voltage of 3.0-4.0V. A soft-program pulse uses a wordline voltage of approximately 2.5V and a bitline voltage of approximately 3.0V. During the soft program verify process 134, all of the memory cells in the block are checked to determine whether any over-erased memory cells remain after the application of the soft-program pulse. If the number of over-erased memory cells in the block is less than or equal to a predetermined number, e.g., zero, the block is regarded as passing the soft program verify process 134. If the block fails to pass soft program verify process 134, soft program process 132 is performed again. The soft program cycle 130 is performed successively until the block passes the soft program verify process 134.
In step 140, if there is another block which needs to be erased, pre-program cycle 110, erase cycle 120, and soft program cycle 130 of the conventional block erase operation are performed in sequence to erase the next block. In this manner, the conventional “soft program” operation is performed to correct over-erased memory cells in all blocks which are erased in the FLASH memory.
When performing the conventional “soft programming” operation, substantial time is required to successfully correct the over-erased memory cells using the conventional soft programming cycle. There is thus a general need in the art for a block erase method for use in a non-volatile memory to reduce the time and/or steps required to erase blocks of the non-volatile memory.